1. Field of the Invention
The present invention relates to a data readout circuit and a semiconductor memory device, and particularly to a data readout circuit for reading data out from a memory cell of a data readout object and to a semiconductor memory device comprising the said data readout circuit.
2. Description of the Related Art
There is a disclosure of a sense amplifier circuit (a current source type sense amplifier circuit) relative to the data readout from a semiconductor memory cell such as an EPROM and the like in the publication of Japanese Patent No. 2513795, the sense amplifier circuit having functions for applying a constant voltage to a data line connected to the semiconductor memory cell and for detecting a current value sufficient to keep a constant voltage in said data line. For example, as shown in FIG. 15A, the sense amplifier circuit 200 disclosed in the particular Japanese Patent publication comprises: a PMOS (P-channel Metal Oxide Semiconductor) transistor 202 having a source connected to the power supply Vcc, a gate to which the bias voltage VBIASP is supplied via the bias voltage input terminal, and a drain connected to the output terminal OUTB; a NMOS (N-channel Metal Oxide Semiconductor) transistor 204 having a drain connected to a drain of the PMOS transistor 202, and a source connected to the input terminal BL; and an operational amplifier 206 having an inversion input terminal connected to the drain of the NMOS transistor 204, a non-inversion input terminal to which the reference voltage VBLREF is supplied via the reference voltage input terminal, and an output terminal connected to the gate of the NMOS transistor 204.
Besides a function similar to the sense amplifier circuit 200 may be realized by a sense amplifier circuit 210 as shown in FIG. 15B which comprises: a PMOS transistor 212 having a source connected to the power supply Vcc, a gate to which the bias voltage VBIASP is supplied via the bias voltage input terminal, and a drain connected to the output terminal OUTB; a PMOS transistor 214 having a source connected to a drain of the PMOS transistor 212, and a drain connected to the input terminal BL; and an operational amplifier 216 having a non-inversion input terminal connected to a drain of the PMOS transistor 214, an inversion input terminal to which the reference voltage VBLREF is supplied via the reference voltage input terminal, and an output terminal connected to a gate of the PMOS transistor 214.
The sense amplifier circuits 200 are connected to the semiconductor memory cell so as to enable to readout data from the semiconductor memory cell since each of the sense amplifier circuits 200 is used as the readout sense amplifier circuit READAMPn (n=0, 1, . . . ) and the reference sense amplifier circuit REFAMP in the amplifier block circuit 220 as shown in FIG. 16. Namely, the bias voltage VBIASP is supplied to each of the sense amplifier circuits 200 via the bias voltage supply line connected to the bias voltage input terminal as well as the reference voltage VBLREF is supplied to each of the sense amplifier circuits 200 via the reference voltage supply line connected to the reference voltage input terminal. In addition, the sense amplifier circuit 200 constituting the readout sense amplifier circuit READAMPn comprises: an input terminal BL connected to the drain terminal of the semiconductor memory cell via the bit line (the data line) BLn; and an output terminal OUTB connected to the inversion input terminal of the operational amplifier 222n. In addition, the sense amplifier circuit 200 constituting the reference sense amplifier circuit REFAMP comprises: an input terminal BL in which the reference outflow current IBLR flows; and output terminals OUTB connected to the non-inversion input terminals of the operational amplifiers 222n respectively. Besides the readout sense amplifier circuit READAMPn and the reference sense amplifier circuit REFAMP may be comprised of the sense amplifier circuit 210 instead of the sense amplifier circuit 200.
When reading data out from the semiconductor memory cell, generally, the drain terminal of the semiconductor memory cell is kept at a constant voltage. In the sense amplifier circuit 200, 210, the operational amplifiers 206, 216 work as a differential amplifier circuit, so that the voltage of the bit line BLn connected to the input terminal BL is kept at the reference voltage VBLREF supplied to the operational amplifier 206, 216 as well as the voltage of the drain terminal of the semiconductor memory cell connected to the bit line BLn is kept at a voltage equivalent to the reference voltage VBLREF. In addition, an electric current flows from the input terminal BL to the bit line BLn at the time of data readout from the semiconductor memory cell, and then an output voltage of the output terminal OUTB decreases according to such a flow of current. However, the amount of reduction of the output voltage changes according to the amount of the outflow current IBL through the bit line BLn and then, the amount of the outflow current IBL, for example, as shown in FIG. 17A, data stored in the semiconductor memory cell of a data readout object (i.e., readout objective data) differ in response to “0” or “1”.
The reference sense amplifier circuit REFAMP of the amplifier block circuit 220 is provided in order to judge an amount of the outflow current IBL (an amount of reduction of the output voltage) corresponding to “0” or “1” of the readout objective data. For example as shown in FIG. 17B, the circuit is configured so that the output voltage of the output terminal OUTB (i.e., reference voltage VREF inputted into each operational amplifier 222n) becomes a level equal to the middle voltage both of the output voltage after decreased when the readout objective data is “0” and the output voltage after decreased when the readout objective data is “1”. Besides in FIG. 17B the voltage at the output terminal OUTB is notated as “OUTB” and the voltage at the bit line is notated as “BL” and, the voltages at the bit line are overlapped because there is little difference between the voltages at the bit line in the readout objective data “0” and “1”.
As described above, to set the reference voltage VREF to be equal to the said middle voltage can be realized by setting the reference outflow current IBLR flowing through the input terminal BL of the reference sense amplifier circuit REFAMP equal to the middle amount both of the outflow current IBL when the readout objective data is “1” and the outflow current IBL when the readout objective data is “0”. By this, the readout objective data “0” or “1” may be discriminated on the basis of output from each operational amplifier 222n operating as a differential amplifier.
By the way, in the sense amplifier circuit 200, 210, the greater the outflow current IBL flows through the bit line BL, the greater the output voltage of the output terminal OUTB considerably decreases as described above. Therefore, it is preferable to the operation of each of the PMOS transistor 202 and the NMOS transistor 204 of the sense amplifier circuit 200, and the PMOS transistors 212, 214 of the sense amplifier circuit 210 is performed in the saturation region, in order to improve the voltage gain of the output voltage.
Thus, in the sense amplifier circuit 200, providing that a voltage between a source and a drain of the PMOS transistor 202 is VSDP, the threshold voltage of the PMOS transistor 202 is VTP, a voltage between a drain and a source of the NMOS transistor 204 is VDSN, a voltage between a gate and a source of the NMOS transistor 204 is VGSN, and the threshold voltage of the NMOS transistor 204 is VTN as parameters, then the operations of the PMOS transistor 202 and the NMOS transistor 204 of the sense amplifier circuit 200 in the saturation region can be realized by satisfying the following formula (1) for the PMOS transistor 202 and the following formula (2) for the NMOS transistor 204 respectively:VSDP>Vcc−VBIASP−|VTP|  (1)VDSN>VGSN−VTN   (2).From the formulae (1), (2), the following formula (3) is obtained:VSDP+VDSN>Vcc−VBIASP−|VTP|+VGSN−VTN   (3).In addition, the PMOS transistor 202 and the NMOS transistor 204 are connected in series between the power supply Vcc and the input terminal BL (i.e., bit line BLn), and the voltage of the bit line BLn is maintained at the reference voltage VBLREF. Therefore, the following formula (4) is established:Vcc−VBLREF=VSDP+VDSN   (4).From the formulae (3), (4), the following formula (5) is obtained:VBLREF<VBIASP+|VTP|−VGSN+VTN   ( 5).Accordingly, if the formula (5) is satisfied in the sense amplifier circuit 200 then the PMOS transistor 202 and the NMOS transistor 204 operate in the saturation regions. Such operations can be realized normally by adjusting the bias voltage VBIASP etc. However, it is difficult to satisfy the formula (5) if the power supply Vcc is a relatively low voltage and the reference voltage VBLREF is a relatively high voltage. As a result, the PMOS transistor 202 and the NMOS transistor 204 do not operate in the saturation region, so that fatal inconveniences such as the gain reduction etc. occurs and the voltage at the bit line is not kept at the reference voltage VBLREF or the like.
Furthermore, in the sense amplifier circuit 210, providing that a voltage between a source and a drain of the PMOS transistor 212 is VSDP1, a voltage between a source and a gate of the PMOS transistor 212 is VSGP1, a voltage between a source and a drain of the PMOS transistor 214 is VSDP2, a voltage between a source and a gate of the PMOS transistor 214 is VSGP2 as parameters, then the operations of the PMOS transistors 212, 214 of the sense amplifier circuit 210 in the saturation region can be realized by satisfying the following formula (6) for the PMOS transistor 212 and the following formula (7) for the PMOS transistor 214 respectively:VSDP1>Vcc−VBIASP−|VTP|  (6)VSDP2>VSGP2−|VTP|  (7).From the formulae (6), (7), the following formula (8) is obtained:VSDP1+VSGP2>Vcc−VBIASP−|VTP|+VSGP2−|VTP|  (8).In addition, the PMOS transistor 212, 214 is connected in series between the power supply Vcc and the input terminal BL (i.e., bit line BLn) and the voltage of the bit line BLn is maintained at the reference voltage VBLREF. Therefore, the next formula (9) is established:Vcc−VBLREF=VSDP1+VSDP2   (9).From the formulae (8), (9), the following formula (10) is obtained:VBLREF<VBIASP+2|VTP|−VSGP2   ( 10)Accordingly, if the formula (10) is satisfied in the sense amplifier circuit 210, then the PMOS transistors 212, 214 operate in the saturation regions. Such operations can be realized normally by adjusting the bias voltage VBIASP etc. However, it is difficult to satisfy the formula (5), similarly to the sense amplifier circuit 200, if the power supply Vcc is a relatively low voltage and the reference voltage VBLREF is a relatively high voltage. As a result, the PMOS transistors 212, 214 do not operate in the saturation region, so that fatal inconveniences such as the gain reduction etc. occurs and the voltage at the bit line BL is not kept at the reference voltage VBLREF or the like.